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ASIC / SoC FPGA Platform
ASIC/SoC Chipset Test BED EVB Platform
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ASIC / SoC FPGA Platform
ASIC/SoC development should satisfy the standard initially set as the goal early in each stage in order to minimize the burden of opportunity cost and to secure the opportunity of the customer's market entry and competitiveness compared to the price. The performance of the target chip should be checked before starting the manufacturing process by utilizing the verification system in the RTL design stage, and the verification of the final finished chip compared to the target performance in the initial design stage is needed. The most generalized and the efficient method is the verification system using FPGA, and the design with the platform decided by the verification system to be utilized in the final finished chip verification process is the system used in the initial RTL verification stage. The ASIC/SoC FPGA platform provided for a customer by Semisolution is the optimal verification system and the customer can secure verification efficiency and economical feasibility.
Discussion on the development range
      - FPGA B/D design part (without RTL Coding)
      - FPGA B/D + RTL coding
      - FPGA B/D + RTL coding + Windows device driver development
Discussing the developed FPGA B/D verification method
      - Determining the results on the test method and completion by defining the I/O for each function
FPGA B/D design verification method
      - Generating the signal to verify the I/O function at the FPGA B/D level
      - Checking the I/O results equivalent to the simulation results and verifying the reoccurrence
      - Applying the verification method according to customer requirements and completing the project