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| High Advanced Process(UMC) |
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| UMC is a leading global semiconductor foundry that manufactures advanced system-on-chip (SoC) designs for applications spanning every major sector of the IC industry. UMC¡¯s customer-driven foundry solutions are based on the strength of the company¡¯s advanced technologies, which include production proven 90nm, 65nm, mixed signal/RFCMOS, and a wide range of specialty technologies. Production is supported through 10 wafer manufacturing facilities that include two advanced 300mm FABs; FAB 12A in Taiwan and Singapore-based FAB 12i are both in volume production for a variety of customer products. The company employs approximately 13,000 people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States. |
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| As a world leading pure-play foundry, UMC offers comprehensive design resources that support our cutting-edge process technologies. Silicon verified libraries (standard cells and I/Os) optimized to our technologies are available free-of-charge from several leading vendors. UMC has also worked internally and with third party partners to deliver an extensive portfolio of IP that are optimized for portability and cost. These range from fundamental IP such as cell and I/O libraries to more complex processor and application- specific standard cores. And, because silicon verification is such a critical issue for customers' deep sub-micron designs, UMC has launched the Silicon Shuttle multi-chip test wafer program. UMC also makes available SRAM memory compilers to support all of its mainstream processes. |
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| FEATURE |
0.13§ |
0.15§ |
0.18§ |
0.25§ |
0.35§ |
| STANDARD CELL |
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| STANDARD I/O |
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| ANALOG I/O |
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| SFAM COMPILER |
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| REGISTER FILE |
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| ROM |
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| eOTP |
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| eFUSE |
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| eFLASH/EEPROM |
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| The increasing costs of designing into nanometer technologies means that first-time silicon success has become essential to meeting cost and time to market targets. UMC's design methodology is developed to help customers reach successful silicon in the shortest time possible by utilizing proven reference design flows, the latest design for manufacturing (DFM) solutions, and EDA tools correlated to UMC silicon from leading EDA vendors. The result is a reliable path to silicon that minimizes risk. |
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Features of
Design Flow |
Cadence |
Synopsys |
Magma |
Mentor |
Ansoft |
Springsoft |
| Functional Logic Simulation |
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Schematic
Entry |
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Logic Timing
Analysis |
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Static Timing
Analysis |
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Timing
Closure |
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Signal
Integrity |
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Floor
Planning |
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Physical
Synthesis |
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Multi-Vt
Low Power |
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Multi-Vdd
Low Power |
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Design For
Test |
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Design For
Diagnosis |
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DFM
(double via/ dum met) |
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Circuits
Simulation |
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Power
Analysis |
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Layout
Editor |
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Place &
Route |
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Physical
Verification |
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Formal
Verification |
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Parasitic
Extraction |
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Noise
Analysis |
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RF/CMOS
/EMDM |
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Analog
Mixed Signal |
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| Given the deep sub-micron design challenges that circuit designers are facing, UMC Reference Design Flows provide customers with EDA design methodologies that reduce time-to-market by enabling manufacturability. The UMC Reference Design Flows incorporate 3rd-party EDA vendor's baseline design flows to address issues such as timing closure, signal integrity, power consumption and design for manufacturability and adopt a hierarchical design approach built upon silicon validated process libraries. The UMC Reference Design Flows cover from RTL coding all the way to GDS-II generation and support Cadence, Magma, Mentor and Synopsys EDA tools. All of these tools have been correlated to UMC silicon and can be interchanged for added flexibility. |
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